A 16‐bit, ±10‐V Input Range SAR ADC with a 5‐V Supply Voltage and Mixed‐Signal Nonlinearity Calibration

Digital Calibration of SAR ADC

Four techniques for digital background calibration of SAR ADC are presented and compared. Sub-binary redundancy is the key to the realization of these techniques. Some experimental and simulation results are covered to support the effectiveness of these techniques. Keywords—SAR ADC, digital background calibration, DAC mismatch, bit weight, sub-binary redundancy

Error Canceling Low Voltage SAR - ADC

ACKNOWLEDGMENTS I would like to express my sincere and deep appreciation to my academic advi-sors, Dr. Gabor C. Temes and Dr. Un-Ku Moon, for the research project and excellent academic environment they provided for me. I have been honored and privileged to have worked under their supervision. Without their warm encouragement and academic guidance as well as their generous support, it would be ...

A 12 bit 76MS/s SAR ADC with a Capacitor Merged Technique in 0.18µm CMOS Technology

A new high-resolution and high-speed fully differential Successive Approximation Register (SAR) Analog to Digital Converter (ADC) based on Capacitor Merged Technique is presented in this paper. The main purposes of the proposed idea are to achieve high-resolution and high-speed SAR ADC simultaneously as well. It is noteworthy that, exerting the suggested method the total capacitance and the rat...

A 0.3-V, 37.5-nW 1.5∼6.5-pF-input-range supply voltage tolerant capacitive sensor readout

Global clock calibration for an SAR ADC interface

This paper presents the interface circuit which incorporates the technique of analog value to digital value conversion utilising a self clocking method. The architecture consists of the Globally Asynchronous and Locally Synchronous (GALS) building blocks, where the processing hardware is being realized by the set of smaller slices of similar structure, each running synchronously with independen...